Present complementary metal oxide semiconductor (CMOS) and bipolar-CMOS (BiCMOS) circuits employ electrostatic discharge protection (ESD) circuits to protect against electrostatic discharge due to ordinary human and machine handling. This electrostatic discharge occurs when the semiconductor circuit contacts an object that is charged to a substantially different electrostatic potential of typically several thousand volts. The contact produces a short-duration, high-current transient in the semiconductor circuit. This high current transient may damage the semiconductor circuit through joule heating. Furthermore, high voltage developed across internal components of the semiconductor circuit may damage MOS transistor gate oxide.
Sensitivity of the semiconductor circuit is determined by various test methods. A human body model test circuit is typically used to determine sensitivity of the semiconductor circuit to human handling. A common human body model test circuit includes a 100 pF capacitor and 1500Ω resistor to emulate a human body resistor-capacitor (RC) time constant of 150 nanoseconds. A stress voltage supply connected in series with a current limiting resistor to charge the 100 pF capacitor to a desired stress voltage. The semiconductor device or device under test (DUT) is connected to the test circuit at a predetermined external terminal for a selected test pin combination. In operation, a switch selects a discharge path through the 1500Ω resistor and the DUT. A post stress current-voltage measurement determines whether the DUT is damaged. Although this test effectively emulates electrostatic discharge from a human body, it fails to comprehend other common forms of electrostatic discharge. Moreover, the relatively high resistance discharge path of the test circuit drops most of the stress voltage during the ESD test, thereby producing a low-voltage test at the DUT.
Another common test circuit of the prior art for tests semiconductor circuits under charged device ESD. This circuit is typically used to determine sensitivity of the semiconductor circuit to ESD under automated manufacturing conditions. The test circuit includes a stress voltage supply connected in series with a current limiting resistor. The DUT forms a capacitor above a ground plane that is typically 1-5 pF. The DUT is precharged to a desired test voltage from the stress voltage supply. A small parasitic resistor and parasitic inductor form a discharge path having an RC time constant typically two orders of magnitude less than the tester of FIG. 5. In operation, a switch connects an external terminal of the DUT to the discharge path through parasitic resistor and parasitic inductor. This connection produces a high-voltage, high-current discharge at the DUT.
All of the foregoing ESD test methods may induce destructive voltage and current levels in internal circuits of a semiconductor. One such internal failure mode was reported by Huh et al., “ESD-induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SOC) Designs,” Proceedings of the Fifth Internal Workshop on System-on-Chip for Real-Time Applications, 47-53 (July 2005) and reproduced in Proceedings of the 9th Internal Database Engineering & Application Symposium (IDEAS '05). The reported internal failure occurred at a power domain crossing circuit (PDCC). Multiple power domains are common for complex integrated and may be separately implemented for analog, digital, input/output, or other circuit functions to reduce noise. The power domain crossing circuit includes transmitter and receiver circuits that transfer signals from circuitry in one power domain to circuitry in another power domain.
Referring to FIG. 1A, there is an exemplary power domain crossing circuit of the prior art. A first power domain includes VDD1 bus 102 and VSS1 bus 106. P-channel transistor 116 and N-channel 118 form an inverter connected between VDD1 bus 102 and VSS1 bus 106. The VSS1 bus 106 also includes a metal resistance RM. The first power domain also includes a local power supply protection circuit 110 having an N-channel transistor M1 and a resistor R and capacitor C gate bias circuit. A second power domain includes circuitry powered by VDD2 bus 104 and VSS2 bus 108. P-channel transistor 122 and N-channel 124 form another inverter connected between VDD2 bus 104 and VSS2 bus 108. The second power domain includes a separate local power supply protection circuit 112 having an N-channel transistor M2 and a resistor R and capacitor C gate bias circuit. Bus VSS1 106 is connected to bus VSS2 108 by anti parallel diodes 114 to conduct ESD current during stress testing across the power domains. Alternative power domain designs may omit anti parallel diodes 114 and connect both VSS1 106 and VSS2 108 to a common external terminal or use other isolation means.
In operation, when a sufficient level of positive ESD voltage is applied to VDD1 bus 102 with respect to VSS2 bus 108, the power domain crossing circuit may fail as described with reference to FIG. 1B. Transistor M1 of local power supply protection circuit 110 turns on with the aid of the gate bias circuit to conduct ESD stress current in snapback mode. This typically develops about 7 V across local power supply protection circuit 110 during human body model ESD stress. Here and in the following discussion, voltages are presented by way of explanation of circuit operation and not in a limiting manner. Another 2 V may be developed across metal resistance RM and 1 V across diode 114. A parallel current path between VDD1 bus 102 and VSS2 bus 108 is formed by P-channel transistor 116 and N-channel transistor 124. The gate of P-channel transistor 116 is initially at VSS1 potential during ESD testing. Thus, P-channel transistor 116 is on, and there is approximately 0 V dropped across the source to drain current path. The entire 10 V, therefore, appears across the gate to source terminals of N-channel transistor 124. Gate oxide typically fails at 10 MV/cm. Therefore, failure occurs at the gate to source overlap of N-channel transistor 124 if the gate oxide thickness of less than 10 nm.
Turning now to FIG. 2A, there is another power domain crossing circuit of the prior art as reported by Huh et al. Common reference numerals here and throughout the specification indicate the same circuit elements. Huh et al. improved the previously described power domain crossing circuit by adding N-channel transistor 120 across the gate and source terminals of N-channel transistor 124. Referring to FIG. 2B, this clamp precludes damage voltage levels between the gate and source terminals of N-channel transistor 124 during positive ESD stress of VDD1 bus 102 with respect to VSS2 bus 108. The gate to source voltage N-channel transistor 124 is clamped to approximately 7 V. The remaining 3 V appears across P-channel transistor 116 as a product of channel current and resistance. However, the N-channel transistor clamp 120 increases the load on P-channel transistor 116 and N-channel transistor 118 during normal circuit operation. Additionally, it may degrade ESD performance for positive ESD stress of VSS1 bus 106 with respect to VDD2 bus 104. In view of these limitations, the present inventors have seen a need for further improvement of power domain crossing circuits for both ESD and normal circuit operation.